COA-UNIT-3 Control Unit

 

UNIT-3 Control Unit

 

Instructions

Instructions are a set of machine language instructions that a particular processor understands and executes. A computer performs tasks on the basis of the instruction provided.

An instruction comprises of groups called fields. These fields include:

• The Operation code (Opcode) field which specifies the operation to be performed.
• The Address field which contains the location of the operand, i.e., register or memory location.
• The Mode field which specifies how the operand will be located.

A basic computer has three instruction code formats which are:

1. Memory - reference instruction
2. Register - reference instruction
3. Input-Output instruction

Memory - reference instruction

In Memory-reference instruction, 12 bits of memory is used to specify an address and one bit to specify the addressing mode 'I'.

Register - reference instruction

The Register-reference instructions are represented by the Opcode 111 with a 0 in the leftmost bit (bit 15) of the instruction.

Note: The Operation code (Opcode) of an instruction refers to a group of bits that define arithmetic and logic operations such as add, subtract, multiply, shift, and compliment.

A Register-reference instruction specifies an operation on or a test of the AC (Accumulator) register.

 

 

 

 

Input-Output instruction

Just like the Register-reference instruction, an Input-Output instruction does not need a reference to memory and is recognized by the operation code 111 with a 1 in the leftmost bit of the instruction. The remaining 12 bits are used to specify the type of the input-output operation or test performed.

Ø  Instruction formats

Instruction formats refer to the way instructions are encoded and represented in machine language. There are several types of instruction formats, including zero, one, two, and three-address instructions.

Each type of instruction format has its own advantages and disadvantages in terms of code size, execution time, and flexibility. Modern computer architectures typically use a combination of these formats to provide a balance between simplicity and power.

Instruction Fields

The most common fields are:

·       The operation field specifies the operation to be performed, like addition.

·       Address field which contains the location of the operand, i.e., register or memory location.

·       Mode field which specifies how operand is to be founded.

Types of Instructions

Based on the number of addresses, instructions are classified as:

NOTE:  We will use the X = (A+B)*(C+D) expression to showcase the procedure. 

Zero Address Instructions

These instructions do not specify any operands or addresses. Instead, they operate on data stored in registers or memory locations implicitly defined by the instruction. For example, a zero-address instruction might simply add the contents of two registers together without specifying the register names.

Zero Address Instruction

A stack-based computer does not use the address field in the instruction. To evaluate an expression, it is first converted to reverse Polish Notation i.e. Postfix Notation.

Expression: X = (A+B)*(C+D)
Postfixed : X = AB+CD+*
TOP means top of stack
M[X] is any memory location

PUSH	A	TOP = A
PUSH	B	TOP = B
ADD		TOP = A+B
PUSH	C	TOP = C
PUSH	D	TOP = D
ADD		TOP = C+D
MUL		TOP = (C+D)*(A+B)
POP	X	M[X] = TOP

One Address Instructions

These instructions specify one operand or address, which typically refers to a memory location or register. The instruction operates on the contents of that operand, and the result may be stored in the same or a different location. For example, a one-address instruction might load the contents of a memory location into a register.

This uses an implied ACCUMULATOR register for data manipulation. One operand is in the accumulator and the other is in the register or memory location. Implied means that the CPU already knows that one operand is in the accumulator so there is no need to specify it.

One Address Instruction

Expression: X = (A+B)*(C+D)
AC is accumulator
M[] is any memory location
M[T] is temporary location

LOAD	A	AC = M[A]
ADD	B	AC = AC + M[B]
STORE	T	M[T] = AC
LOAD	C	AC = M[C]
ADD	D	AC = AC + M[D]
MUL	T	AC = AC * M[T]
STORE	X	M[X] = AC

Two Address Instructions

These instructions specify two operands or addresses, which may be memory locations or registers. The instruction operates on the contents of both operands, and the result may be stored in the same or a different location. For example, a two-address instruction might add the contents of two registers together and store the result in one of the registers.

This is common in commercial computers. Here two addresses can be specified in the instruction. Unlike earlier in one address instruction, the result was stored in the accumulator, here the result can be stored at different locations rather than just accumulators, but require more number of bit to represent the address.

Two Address Instruction

Here destination address can also contain an operand.

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

MOV	R1, A	R1 = M[A]
ADD	R1, B	R1 = R1 + M[B]
MOV	R2, C	R2 = M[C]
ADD	R2, D	R2 = R2 + M[D]
MUL	R1, R2	R1 = R1 * R2
MOV	X, R1	M[X] = R1

Three Address Instructions

These instructions specify three operands or addresses, which may be memory locations or registers. The instruction operates on the contents of all three operands, and the result may be stored in the same or a different location. For example, a three-address instruction might multiply the contents of two registers together and add the contents of a third register, storing the result in a fourth register.

This has three address fields to specify a register or a memory location. Programs created are much short in size but number of bits per instruction increases. These instructions make the creation of the program much easier but it does not mean that program will run much faster because now instructions only contain more information but each micro-operation (changing the content of the register, loading address in the address bus etc.) will be performed in one cycle only.

Three Address Instruction

Expression: X = (A+B)*(C+D)
R1, R2 are registers
M[] is any memory location

ADD	R1, A, B	R1 = M[A] + M[B]
ADD	R2, C, D	R2 = M[C] + M[D]
MUL	X, R1, R2	M[X] = R1 * R2

Advantages of Zero-Address, One-Address, Two-Address and Three-Address Instructions

Zero-address instructions

·       Stack-based Operations: In stack-based architectures, where operations implicitly employ the top items of the stack, zero-address instructions are commonly used.

·       Reduced Instruction Set: It reduces the complexity of the CPU design by streamlining the instruction set, which may boost reliability.

·       Less Decoding Complexity: Especially helpful for recursive or nested processes, which are frequently used in function calls and mathematical computations.

·       Efficient in Nested Operations: Less bits are required to specify operands, which simplifies the logic involved in decoding instructions.

·       Compiler Optimization: Because stacks are based on stacks, several algorithms can take use of this to improve the order of operations.

One-address instructions

·       Intermediate Complexity: Strikes a balance between versatility and simplicity, making it more adaptable than zero-address instructions yet simpler to implement than multi-address instructions.

·       Reduced Operand Handling: Compared to multi-address instructions, operand fetching is made simpler by just needing to handle a single explicit operand.

·       Implicit Accumulator: O ften makes use of an implicit accumulator register, which can expedite up some operations’ execution and simplify designs in other situations.

·       Code Density: S maller code in comparison to two- and three-address instructions, which may result in more efficient use of memory and the instruction cache.

·       Efficient Use of Addressing Modes: Can make use of different addressing modes (such indexed, direct, and indirect) to improve flexibility without adding a lot of complexity.

Two-address instructions

·       Improved Efficiency: Allows for the execution of operations directly on memory or registers, which reduces the amount of instructions required for certain activities.

·       Flexible Operand Use: Increases programming variety by offering more options for operand selection and addressing modes.

·       Intermediate Data Storage: May directly store interim results, increasing some algorithms’ and calculations’ efficiency.

·       Enhanced Code Readability: Produces code that is frequently easier to read and comprehend than one-address instructions, which is beneficial for maintenance and troubleshooting.

·       Better Performance: Better overall performance can result from these instructions because they minimize the amount of memory accesses required for certain processes.

Three-address instructions

·       Direct Representation of Expressions: Reduces the need for temporary variables and extra instructions by enabling the direct representation of complicated expressions.

·       Parallelism: Allows for the simultaneous fetching and processing of several operands, which facilitates parallelism in CPU architecture.

·       Compiler Optimization: Makes it possible for more complex compiler optimizations to be implemented, which improve execution efficiency by scheduling and reordering instructions.

·       Reduced Instruction Count: May increase execution performance even with bigger instruction sizes by perhaps lowering the overall number of instructions required for complicated processes.

·       Improved Pipeline Utilization: More information in each instruction allows CPU pipelines to be used more efficiently, increasing throughput overall.

·       Better Register Allocation: Permits direct manipulation of several registers inside a single instruction, enabling more effective usage of registers.

Disadvantages of Zero-Address, One-Address, Two-Address and Three-Address Instructions

Zero-address instructions

·       Stack Dependency: In contrast to register-based architectures, zero-address instructions might result in inefficiencies when it comes to operand access because of their heavy reliance on the stack.

·       Overhead of Stack Operations: Performance might be negatively impacted by the frequent push and pop actions needed to maintain the stack.

·       Limited Addressing Capability: The processing of intricate data structures may become more difficult since they do not directly support accessing memory regions or registers.

·       Difficult to Optimize: Because operand access is implied in stack-based designs, code optimization might be more difficult.

·       Harder to Debug: When compared to register-based operations, stack-based operations might be less obvious and more difficult to debug.

One-address instructions

·       Accumulator Bottleneck: Often uses an accumulator, which can act as a bottleneck and reduce efficiency and parallelism.

·       Increased Instruction Count: Multiple instructions may be needed for complex processes, which would increase the overall number of instructions and code size.

·       Less Efficient Operand Access: There is just one operand that is specifically addressed, which might result in inefficient access patterns and extra data management instructions.

·       Complex Addressing Modes: The instruction set and decoding procedure get more complicated when several addressing modes are supported.

·       Data Movement Overhead: Moving data between memory and the accumulator could need more instructions, which would increase overhead.

Two-address instructions

·       Operand Overwriting: Usually, the result overwrites one of the source operands, which might lead to an increase in the number of instructions needed to maintain data.

·       Larger Instruction Size: Because two-address instructions are bigger than zero- and one-address instructions, the memory footprint may be increased.

·       Intermediate Results Handling: It is frequently necessary to handle intermediate outcomes carefully, which can make programming more difficult and result in inefficiencies.

·       Decoding Complexity: The design and performance of the CPU may be impacted by the greater complexity involved in decoding two addresses.

·       Inefficient for Some Operations: The two-address style could still be inefficient for some tasks, needing more instructions to get the desired outcome.

Three-address instructions

·       Largest Instruction Size: Has the highest memory requirements per instruction, which can put strain on the instruction cache and increase code size.

·       Complex Instruction Decoding: Three addresses to decode adds complexity to the CPU architecture, which might affect power consumption and performance.

·       Increased Operand Fetch Time: Each instruction may execute more slowly if obtaining three operands takes a long period.

·       Higher Hardware Requirements: Has the potential to raise cost and power consumption since it requires more advanced hardware to handle the higher operand handling and addressing capabilities.

·       Power Consumption: Higher power consumption is a crucial factor for devices that run on batteries since it can be caused by more complicated instructions and increased memory utilization.

 

Ø  Instruction Cycle

A program residing in the memory unit of a computer consists of a sequence of instructions. These instructions are executed by the processor by going through a cycle for each instruction.

In a basic computer, each instruction cycle consists of the following phases:

1. Fetch instruction from memory.
2. Decode the instruction.
3. Read the effective address from memory.
4. Execute the instruction.

 

 

1.Fetch:  

The processor copies the instruction data captured from the RAM. 

2. Decode: 

Decoded captured data is transferred to the unit for execution.

3. Execute: 

Instruction is finally executed. The result is then registered in the processor or RAM (memory address). 

Ø  Interrupt SUB-Cycle:

 In interrupt cycle, an interrupt can occur any time during the program execution. Whenever it is caused, a series of events of events take place so that the instruction fetch execute cycle can again resume after the OS calls the routine to handle the interrupt. This cycle of fetching a new instruction, decoding it and finally executing it continues until the computer is turned off.

 

 

 

 

To accommodate interrupts, an interrupt cycle is added to the instruction cycle as shown in figure. In the interrupt cycle, the processor checks to see if any interrupts have occurred, indicated by the presence of an interrupt signal. If no interrupts are pending, the processor proceeds to the fetch cycle and fetches the next instruction of the current program. If an interrupt is pending, the processor does the following:

 

(i)             It suspends execution of the current program being executed and saves its context. This means saving the address of the next instruction to be executed and any other data relevant to the processor's current activity.

(ii)            (ii)  It sets the program counter to the starting address of an interrupt handler routine. The processor now proceeds to the fetch cycle and fetches the first instruction in the interrupt handler program, which will service the interrupt. The interrupt handler program is generally part of the operating system. Typically, this program determines the nature of the interrupt and performs whatever actions are needed.

 

Ø  Micro Operation

 Micro-operation refers to the smallest tasks performed by the CPU’s control unit. These micro-operations helps to execute complex instructions. They involve simple tasks like moving data between registers, performing arithmetic calculations, or executing logic operations. Each micro-operation is completed in a single clock cycle.

Below Figure shows the concept being discussed here.

Micro-operations are small tasks performed inside the CPU. These tasks use data stored in the CPU’s registers to do basic operations like math or logic tasks. They also help move data between registers or between memory and registers.

Examples of Micro-Operations

1.      Load: Moves data from memory into a register.

2.      Store: Saves data from a register back into memory.

3.      Add: Adds two values and stores the result in a register.

4.      Subtract: Subtracts one value from another and stores the result in a register.

5.      AND: Performs a logical AND operation on two values and stores the result in a register.

6.      OR: Performs a logical OR operation on two values and stores the result in a register.

7.      NOT: Reverses the bits of a value and stores the result in a register.

8.      Shift: Moves the bits of a value to the left or right within a register.

9.      Rotate: Rotates the bits of a value left or right in a register.

How Micro-Operations Work?

Micro-operations are combined to perform more complex instructions. For example, an addition instruction might involve several micro-operations:

·       First, a load operation to move values into registers.

·       Then, an add operation to perform the calculation.

·       Finally, a store operation to save the result in memory

 

Ø  Execution of a Complete Instructions:

The execution of instructions refers to the process that the CPU (Central Processing Unit) follows to execute machine-level instructions, typically in the form of assembly language or binary code. This process involves several stages that ensure that the instruction is properly fetched, decoded, and executed.

Here's a breakdown of the typical steps involved in the execution of a complete instruction in computer organization, focusing on the "fetch-decode-execute" cycle:

1. Fetch Stage:

1.      Instruction Fetch: The instruction to be executed is fetched from memory.

2.      The CPU contains a Program Counter (PC), which holds the address of the next instruction to be executed.

3.      The PC points to the memory location of the instruction.

4.      The CPU then loads the instruction from the memory into the Instruction Register (IR).

5.      After fetching the instruction, the Program Counter is incremented (or updated) to point to the next instruction.

2. Decode Stage:

1.      Instruction Decode: The CPU decodes the fetched instruction to understand what operation needs to be performed.

2.      The control unit (CU) interprets the instruction in the Instruction Register (IR).

3.      The instruction is usually in machine code, and the control unit identifies the opcode (operation code) to determine the type of instruction (e.g., add, subtract, move data, jump).

4.      It also identifies the operands (data or addresses) that will be used by the instruction. The operands might be in registers, memory locations, or immediate values.

5.      If the instruction involves a memory address, the effective address may need to be calculated (e.g., using index registers, or base and offset addressing).

3. Execute Stage:

1.      Execute: The CPU performs the operation specified by the decoded instruction.

2.      If the instruction is an arithmetic or logic operation, the Arithmetic Logic Unit (ALU) performs the operation on the operands.

3.      If it's a memory operation (e.g., load or store), the CPU accesses the memory to read or write data.

4.      If the instruction involves a jump or branch, the CPU may modify the Program Counter based on the instruction (e.g., jump to a new address).

5.      For I/O operations, the CPU interacts with peripheral devices as per the instruction.

4. Memory Access (if needed):

1.      For load or store operations, there may be a separate stage to interact with memory:

2.      If the instruction is a load, data is fetched from memory and stored in a register.

3.      If the instruction is a store, data from a register is written to memory.

5. Write-back (if needed):

1.      Write-back: After the execution stage, the results of the computation (if any) are written back to the destination register or memory.

2.      For most arithmetic operations, the result is stored in a register.

3.      For memory instructions, data may be written back to memory.

6. Repeat Cycle:

The CPU then returns to the fetch stage and continues this cycle, fetching and executing the next instruction from memory until the program ends.

 

 

Example of a Complete Instruction Execution:

Let's look at a simple example using a basic arithmetic operation, such as adding two numbers in registers.

Ø  Fetch: The CPU fetches the instruction ADD R1, R2, R3 (add the contents of registers R2 and R3, and store the result in R1).

1.      The Program Counter (PC) points to the memory location of the ADD instruction.

2.      The instruction is fetched and stored in the Instruction Register (IR).

Ø  Decode: The control unit decodes the instruction.

1.      The opcode ADD is recognized.

2.      The operands are identified: register R2 and R3.

3.      The control unit prepares the ALU for an addition operation and sets up the necessary control signals.

Ø  Execute: The ALU performs the addition.

1.      The contents of registers R2 and R3 are added together.

2.      The result is stored in a temporary register or directly placed into R1.

Ø  Write-back: The result from the ALU (R2 + R3) is written back to register R1.

Ø  Repeat: The program continues to the next instruction, and the cycle repeats.

 

Ø  Program Control Instructions

 

Program Control Instructions are the machine code instructions which are used to control the flow of execution of instructions in the processor domain. These are important in instilling on the processor how to execute a certain task, access different programs and control the decision making on the basis of some conditions. They are commonly used in assembly language and generated by high level language which is compiled into machine code form to enable the processor act in the desired manner.

Types of Program Control Instructions

1. Compare Instruction

Compare instruction is specifically provided, which is similar to a subtract instruction except the result is not stored anywhere, but flags are set according to the result. 

Example:
CMP R1, R2 ;

2. Unconditional Branch Instruction

It causes an unconditional change of execution sequence to a new location. 

Example:
JUMP L2
Mov R3, R1 goto L2

3. Conditional Branch Instruction

A conditional branch instruction is used to examine the values stored in the condition code register to determine whether the specific condition exists and to branch if it does. 

Example:
Assembly Code : BE R1, R2, L1
Compiler allocates R1 for x and R2 for y
High Level Code: if (x==y) goto L1;

4. Subroutines

A subroutine is a program fragment that lives in user space, performs a well-defined task. It is invoked by another user program and returns control to the calling program when finished. 

Example:
CALL and RET

5. Halting Instructions

·       NOP Instruction – NOP is no operation. It cause no change in the processor state other than an advancement of the program counter. It can be used to synchronize timing. 
 

·       HALT – It brings the processor to an orderly halt, remaining in an idle state until restarted by interrupt, trace, reset or external action.  

6. Interrupt Instructions

Interrupt is a mechanism by which an I/O or an instruction can suspend the normal execution of processor and get itself serviced. 

·       RESET – It reset the processor. This may include any or all setting registers to an initial value or setting program counter to standard starting location.

·       TRAP – It is non-maskable edge and level triggered interrupt. TRAP has the highest priority and vectored interrupt.

·       INTR – It is level triggered and maskable interrupt. It has the lowest priority. It can be disabled by resetting the processor.

 

Ø  Reduced Instruction Set Architecture (RISC)

The main idea behind this is to simplify hardware by using an instruction set composed of a few basic steps for loading, evaluating, and storing operations just like a load command will load data, a store command will store the data.

Characteristics of RISC

·       Simpler instruction, hence simple instruction decoding.

·       Instruction comes undersize of one word.

·       Instruction takes a single clock cycle to get executed.

·       More general-purpose registers.

·       Simple Addressing Modes.

·       Fewer Data types.

·       A pipeline can be achieved.

Advantages of RISC

·       Simpler instructions: RISC processors use a smaller set of simple instructions, which makes them easier to decode and execute quickly. This results in faster processing times.

·       Faster execution: Because RISC processors have a simpler instruction set, they can execute instructions faster than CISC processors.

·       Lower power consumption: RISC processors consume less power than CISC processors, making them ideal for portable devices.

Disadvantages of RISC

·       More instructions required: RISC processors require more instructions to perform complex tasks than CISC processors.

·       Increased memory usage: RISC processors require more memory to store the additional instructions needed to perform complex tasks.

·       Higher cost: Developing and manufacturing RISC processors can be more expensive than CISC processors.

Complex Instruction Set Architecture (CISC)

The main idea is that a single instruction will do all loading, evaluating, and storing operations just like a multiplication command will do stuff like loading data, evaluating, and storing it, hence it’s complex.

Characteristics of CISC

·       Complex instruction, hence complex instruction decoding.

·       Instructions are larger than one-word size.

·       Instruction may take more than a single clock cycle to get executed.

·       Less number of general-purpose registers as operations get performed in memory itself.

·       Complex Addressing Modes.

·       More Data types.

Advantages of CISC

·       Reduced code size: CISC processors use complex instructions that can perform multiple operations, reducing the amount of code needed to perform a task.

·       More memory efficient: Because CISC instructions are more complex, they require fewer instructions to perform complex tasks, which can result in more memory-efficient code.

·       Widely used: CISC processors have been in use for a longer time than RISC processors, so they have a larger user base and more available software.

Disadvantages of CISC

·       Slower execution: CISC processors take longer to execute instructions because they have more complex instructions and need more time to decode them.

·       More complex design: CISC processors have more complex instruction sets, which makes them more difficult to design and manufacture.

·       Higher power consumption: CISC processors consume more power than RISC processors because of their more complex instruction sets.

 

Ø  Pipelining

 Pipelining is the process of accumulating instruction from the processor through a pipeline. It allows storing and executing instructions in an orderly process. It is also known as pipeline processing. Pipelining is a technique where multiple instructions are overlapped during execution. Pipeline is divided into stages and these stages are connected with one another to form a pipe like structure. Instructions enter from one end and exit from another end. Pipelining increases the overall instruction throughput. In pipeline system, each segment consists of an input register followed by a combinational circuit. The register is used to hold data and combinational circuit performs operations on it. The output of combinational circuit is applied to the input register of the next segment.

 

Pipeline system is like the modern day assembly line setup in factories. For example in a car manufacturing industry, huge assembly lines are setup and at each point, there are robotic arms to perform a certain task, and then the car moves on ahead to the next arm.

Types of Pipeline It is divided into 2 categories:

1. Arithmetic Pipeline

2. Instruction Pipeline

Ø  Arithmetic Pipeline

Arithmetic pipelines are usually found in most of the computers. They are used for floating point operations, multiplication of fixed point numbers etc

. For example: The input to the Floating Point Adder pipeline is:

X = A*2^a

Y = B*2^b

Here A and B are mantissas (significant digit of floating point numbers), while a and b are exponents.

 The floating point addition and subtraction is done in 4 parts:

1. Compare the exponents.

 2. Align the mantissas.

3. Add or subtract mantissas

4. Produce the result.

Registers are used for storing the intermediate results between the above operations.

Ø  Instruction Pipeline

 In this a stream of instructions can be executed by overlapping fetch, decode and execute phases of an instruction cycle. This type of technique is used to increase the throughput of the computer system. An instruction pipeline reads instruction from the memory while previous instructions are being executed in other segments of the pipeline. Thus we can execute multiple instructions simultaneously. The pipeline will be more efficient if the instruction cycle is divided into segments of equal duration.

Ø  hardwired and micro-programmed

Introduction :

The control unit is responsible for directing the flow of data and instructions within the CPU. There are two main approaches to implementing a control unit: hardwired and micro-programmed.

A hardwired control unit is a control unit that uses a fixed set of logic gates and circuits to execute instructions. The control signals for each instruction are hardwired into the control unit, so the control unit has a dedicated circuit for each possible instruction. Hardwired control units are simple and fast, but they can be inflexible and difficult to modify.

On the other hand, a micro-programmed control unit is a control unit that uses a microcode to execute instructions. The microcode is a set of instructions that can be modified or updated, allowing for greater flexibility and ease of modification. The control signals for each instruction are generated by a microprogram that is stored in memory, rather than being hardwired into the control unit.

1.      Hardwired Control Unit: The control hardware can be viewed as a state machine that changes from one state to another in every clock cycle, depending on the contents of the instruction register, the condition codes, and the external inputs. The outputs of the state machine are the control signals. The sequence of the operation carried out by this machine is determined by the wiring of the logic elements and hence named “hardwired”. 

·       Fixed logic circuits that correspond directly to the Boolean expressions are used to generate the control signals.

·       Hardwired control is faster than micro-programmed control.

·       A controller that uses this approach can operate at high speed.

·       RISC architecture is based on the hardwired control unit

2.      Micro-programmed Control Unit –  

·       The control signals associated with operations are stored in special memory units inaccessible by the programmer as Control Words.

·       Control signals are generated by a program that is similar to machine language programs.

·       The micro-programmed control unit is slower in speed because of the time it takes to fetch microinstructions from the control memory.

Some Important Terms

1.      Control Word: A control word is a word whose individual bits represent various control signals.

2.      Micro-routine: A sequence of control words corresponding to the control sequence of a machine instruction constitutes the micro-routine for that instruction.

3.      Micro-instruction: Individual control words in this micro-routine are referred to as microinstructions.

4.      Micro-program: A sequence of micro-instructions is called a micro-program, which is stored in a ROM or RAM called a Control Memory (CM).

5.      Control Store: the micro-routines for all instructions in the instruction set of a computer are stored in a special memory called the Control Store.

 

 

 

 

The differences between hardwired and micro-programmed control units:

	Hardwired Control Unit	Micro-programmed Control Unit
Implementation	Fixed set of logic gates and circuits	Microcode stored in memory
Flexibility	Less flexible, difficult to modify	More flexible, easier to modify
Instruction Set	Supports limited instruction sets	Supports complex instruction sets
Complexity of Design	Simple design, easy to implement	Complex design, more difficult to implement
Speed	Fast operation	Slower operation due to microcode decoding
Debugging and Testing	Difficult to debug and test	Easier to debug and test
Size and Cost	Smaller size, lower cost	Larger size, higher cost
Maintenance and Upgradability	Difficult to upgrade and maintain	Easier to upgrade and maintain

 

 

Types of Micro-programmed Control Unit – Based on the type of Control Word stored in the Control Memory (CM), it is classified into two types : 

1. Horizontal Micro-programmed Control Unit : 
The control signals are represented in the decoded binary format that is 1 bit/CS. Example: If 53 Control signals are present in the processor then 53 bits are required. More than 1 control signal can be enabled at a time. 

·       It supports longer control words.

·       It is used in parallel processing applications.

·       It allows a higher degree of parallelism. If degree is n, n CS is enabled at a time.

·       It requires no additional hardware(decoders). It means it is faster than Vertical Microprogrammed.

·       It is more flexible than vertical microprogrammed

2. Vertical Micro-programmed Control Unit : 
The control signals are represented in the encoded binary format. For N control signals- Log2(N) bits are required.  

·       It supports shorter control words.

·       It supports easy implementation of new control signals therefore it is more flexible.

·       It allows a low degree of parallelism i.e., the degree of parallelism is either 0 or 1.

·       Requires additional hardware (decoders) to generate control signals, it implies it is slower than horizontal microprogrammed.

·       It is less flexible than horizontal but more flexible than that of a hardwired control unit.

 

Ø  Micro Instructions Sequencer

Micro Instructions Sequencer is a combination of all hardware for selecting the next micro-instruction address. The micro-instruction in control memory contains a set of bits to initiate micro-operations in computer registers and other bits to specify the method by which the address is obtained.

Implementation of Micro Instructions Sequencer

·       Control Address Register(CAR) : Control address register receives the address from four different paths. For receiving the addresses from four different paths, Multiplexer is used.

·       Multiplexer : Multiplexer is a combinational circuit which contains many data inputs and single data output depending on control or select inputs.

·       Branching : Branching is achieved by specifying the branch address in one of the fields of the micro instruction. Conditional branching is obtained by using part of the micro-instruction to select a specific status bit in order to determine its condition.

·       Mapping Logic : An external address is transferred into control memory via a mapping logic circuit.

·       Incrementer : Incrementer increments the content of the control address register by one, to select the next micro-instruction in sequence.

·       Subroutine Register (SBR) : The return address for a subroutine is stored in a special register called Subroutine Register whose value is then used when the micro-program wishes to return from the subroutine.

·       Control Memory : Control memory is a type of memory which contains addressable storage registers. Data is temporarily stored in control memory. Control memory can be accessed quicker than main memory.

 

Ø  Horizontal Micro-programmed Control unit

With the help of decoded binary format, we can represent the control signals in the horizontal micro-programmed control unit, i.e., 1bit/CS. Here, n bit encoding is needed for 'n' control signals. With the help of a single control point, each bit is identified in the horizontal micro-programmed CU. This Control point is used to show that the corresponding micro-operation is going to be executed. In this control unit, every micro-program needs less number of micro-instructions. The several resources can be controlled simultaneously with the help of each and every micro-instruction. It also has a bigger advantage, i.e., it has the ability to utilize more efficient hardware.

A higher degree of parallelism is provided by the horizontal CU. This parallelism contains a separate control field and a minimum number of encoding. In the horizontal CU, the task to develop the micro-programs with the help of using resources efficiently and optimally is very complex. Each control bit in the horizontal micro-programmed control unit is independent to each other. That's why this CU provides great flexibility. The horizontal microinstruction contains more information as compared to the vertical microinstruction because horizontal microinstruction contains a greater length.

Fig: Horizontal Microcode

Vertical Micro-programmed CU

In contrast to the Horizontal micro-programmed CU, a higher degree of encoding and variable format can be applied in the vertical micro-programmed control unit. With the help of encoded binary format, we can represent the control signals in the vertical micro-programmed CU. Here, log2n bit encoding is needed for 'n' control signals. A single micro-operation is represented by every vertical micro-instruction. With the help of vertical CU, we can shorten the length of microinstruction as well as prevent the length of microinstruction from being directly affected by the increasing memory capacity.

The microinstruction is performed with the help of a code, and this code will be translated into the individual control signals with the help of a decoder. Because here we only specified the micro-operation that will be performed and the fields of microinstruction are fully utilized. There are basically 4 to 6 fields, and these fields approximately require 16 to 32 bits per instruction. As compared to the horizontal micro-programmed, we can easily write the vertical micro-programmed. Same as the conventional machine language format, the vertical microinstruction also contains a few operands and one operation. So we can easily use the vertical microinstruction for micro-programming.

Fig: Vertical Microcode

Differences between Horizontal and Vertical Micro-programmed CU

There are various differences between the vertical programmed CU and horizontal programmed CU, which are described as follows:

Horizontal Micro-programmed CU	Vertical Micro-programmed CU
This control unit is able to support longer control words.	This control unit is able to support shorter control words.
In this CU, we don't need any type of additional hardware.	In this CU, we need additional hardware to generate the control signals. These types of hardware must be in the form of decoders.
Compared to the vertical micro-programmed control unit, this control unit is less flexible.	Compared to the horizontal micro-programmed control unit, this control unit is more flexible.
Compared to the vertical micro-programmed control unit, this control unit is faster.	Compared to the horizontal micro-programmed control unit, this control unit is slower.
Compared to the vertical micro-programmed control unit, this control unit makes less use of ROM encoding.	Compared to the horizontal micro-programmed control unit, this control unit makes more use of ROM encoding so that it can reduce the control world's length.
A higher degree of parallelism is allowed by the horizontal micro-programmed CU. If there are is 'n' number of degrees, n control signals will be enabled at a time.	The low degree of parallelism is allowed by the vertical micro-programmed CU. That means there can either be 0 or 1 degree of parallelism.
The horizontal microinstruction is used by the horizontal micro-programmed CU. Here control line is attacked with every bit of the control field.	The vertical microinstruction is used by the vertical micro-programmed CU. Here each action will be performed with the help of a code, and this code will be translated into the individual control signals with the help of a decoder.